Current integrated circuit (IC) testing techniques utilize methods that require careful alignment of IC components (packages) during testing. In a testing environment, alignment of a contactor array of a testing equipment (e.g., residing on a printed circuit board (PCB)) to an interconnect array of a package (e.g., a bottom package of the Package-on-Package (PoP) configuration) may be done using passive mechanical alignment, which may involve referencing physical edges of the package. However, current top side interconnect pitches (e.g., in the PoP configuration) may be scaled down from the current 0.4 mm to 0.2 mm and lower. In view of further scaling of IC components, current alignment methodologies may not be able to yield desired alignment accuracy, which may affect quality of testing of IC components.